1. Field of the Invention
This invention relates to a bit compression circuit used for a delta sigma type digital-to-analog converter (D/A converter) applicable to audio apparatus, etc., for providing high conversion accuracy by oversampling.
2. Description of the Related Art
With digital audio apparatus such as a compact disk player, analog sound is sampled at a predetermined frequency for recording as digital data of an appropriate number of bits. In a play mode, digital data read from record media such as a compact disk is restored to analog signals by a D/A converter for reproducing sound as sound signals through an amplifier and a loudspeaker. In the play mode, it is desired to minimize a D/A conversion error for inhibiting distortion of regenerative signals. Various D/A conversion systems have been designed for providing high conversion accuracy to meet this demand.
FIG. 1 is a schematic block diagram of a delta sigma (.DELTA..SIGMA.)type D/A converter.
A bit compression circuit 1 receives, for example, 16-bit digital data DG1 and converts it into 3-bit digital data DG2 for output. In the data conversion, the bit compression circuit 1 oversamples the digital data DG1 at a frequency (48 fs) provided by multiplying a sampling frequency fs by 48, and again quantizes at seven stages of .+-.3 (-3, -2, . . . , 0, . . . +3) so as to provide the 3-bit digital data DG2. At this time, quantization noise, namely, an error of the digital data DG2 compared to the digital data DG1 is biased to the high frequency band side by a so-called noise shaping loop for feeding back an error incurred at the conversion steps in sequence into the input digital data DG1. Thus, quantization noise in a low frequency band is reduced drastically, and most of the quantization noise is ignored by passing data through a low-pass filter. To feed back the quantization noise at the frequency 48 fs, an adder which adds the fed-back quantization noise also operates at 48 fs and the output data frequency of the bit compression circuit 1 also becomes 48 fs.
When digital data DG2 of three bits is input to a pulse width modulation circuit 2, eight clocks are set as the data conversion time to convert a 3-bit data piece. The 3-bit data value determines which of seven "1" signals are active during the eight clock cycles period, in relation to the 3 bit value. For example, if the 3-bit data value is 3, "1" signals are output for the first 3-clock periods within the eight clocks. That is, "1" signals are output for the period of as many clocks as the value of digital data DG2 and "0" signals are output for the remaining period within eight clocks. A sequence of eight 1-bit digital data DG3 pieces (a sequence of eight signals of "1" and "0") is provided corresponding to the digital data DG2. The digital data DG3 is passed through the analog low-pass filter 3 made up of an RC circuit, etc., to remove the high frequency component, and is then output to the next-stage circuit as an analog signal AN having a level corresponding to the input digital signal value. If a time constant at the analog low-pass filter 3 is made small, preferably the pulse width modulation circuit 2 outputs "1" and "0" signals alternately in order to output DC signals at a predetermined level.
FIG. 2 is a block diagram showing the configuration of the bit compression circuit 1 adopting a quadratic noise shaping loop.
A quantization circuit 4 evaluates signal levels indicated by 16-bit digital data DG1 at seven stages of .+-.3, and outputs 3-bit digital data DG2 corresponding to them. Input data and output data of the quantization circuit 4 are fed into an adder 5 where the data output from the quantization circuit 4 is subtracted from the data input to the quantization circuit 4 for calculation of data representing quantization noise. This quantization noise representation data is fed into a delay circuit 6 for a delay as long as one sampling period before it is input to a second delay circuit 7 and a multiplier 8. Then, the output of the delay circuit 7 is fed into an adder 9 for subtraction from digital data DG1, and the output of the multiplier 8 where a multiplication factor is set to 2 is fed into an adder 10 which then adds it to output of the adder 9. Output of the adder 10 is fed into the quantization circuit 4.
Assuming that the digital data DG1 and DG2 are X and Y, that outputs of the adders 10 and 9 are A and B, and that quantization noise at the quantization circuit 4 is N, output of the adder 5 becomes -N and a unit delay is represented by a complex number Z.sup.-1 in Z conversion. Therefore, the following three expressions are true: EQU Y=A+N EQU B-2N.times.Z.sup.-1 =A EQU X+N.times.Z.sup.-2 =B
When A and B are eliminated from these expressions, the output Y with respect to the input X becomes EQU Y=X+N.times.(1-Z.sup.-1).sup.2
This indicates a quadratic noise shaping operation.
In contrast, a bit compression circuit adopting a cubic noise shaping loop contains a delay circuit 11, a multiplier 12, and an adder 13 which are added to the input side of a bit compression circuit forming a quadratic noise shaping loop, as shown in FIG. 3. Output of a delay circuit 7 is fed into the delay circuit 11 and the multiplier 12. Output of the delay circuit 11 is fed into the adder 13 which then adds it to digital data DG1. Output of the multiplier 12 is fed into an adder 9 for subtraction from output of the adder 13. Multiplication factor of both multipliers 8 and 12 is set to "3".
Assuming that the output of the adder 13 is C, the following four expressions are true: EQU Y=A+N EQU B-3N.times.Z.sup.-1 =A EQU C+3N.times.Z.sup.-2 =B EQU X-N.times.Z.sup.-3 =C
as in the circuit shown in FIG. 2. Eliminating A, B, and C from these expressions results in EQU Y=X+N.times.(1-Z.sup.-1).sup.3
This indicates a cubic noise shaping operation.
FIG. 4 shows a bit compression circuit adopting a linear noise shaping loop. As shown in the figure, the delay circuit 7, the multiplier 8, and the adder 9 shown in FIG. 2 are omitted. The bit compression circuit accomplishes a linear noise shaping operation of EQU Y=X+N.times.(1-Z.sup.-1)
For the characteristics of a noise shaping loop of degree n represented by Y=X+N.times.(1-Z.sup.-1).sup.n, the higher the noise shaping degree, the less the noise constituent because normally .vertline.Z.sup.-1 .vertline. is smaller than 1. However, since a noise shaping loop of a high degree increases in the bias of the noise constituent toward a high frequency band, a sharp characteristic is required for the low-pass filter 3 to remove noise in the high frequency band. Therefore, the noise shaping loop degree is set high for the purpose of inhibiting noise in a low frequency band; it is set low for the purpose of inhibiting noise in a high frequency band.
Then, there is a demand to change the noise shaping loop degree according to applications. However, a delta sigma type D/A converter for which the noise shaping loop degree is set at the circuit design stage has a fixed conversion characteristic and is applicable to limited applications, thus lacks versatility and is high in cost.
If the number of bits of digital data DG2 output from the quantization circuit 4 is increased, quantization noise at the quantization circuit 4 is decreased and noise can be reduced without making the noise shaping loop degree high. However, as the number of bits of output data of the quantization circuit 4 increases, high speed operation is required for the pulse width modulation circuit 2 where as many clocks as the number of quantization steps must be set within one sampling period. If data consists of three bits, eight clocks are required; if it consists of four bits, 16 clocks are required. As a result, the D/A converter depends on how fast the circuit components operate.